Silicon-controlled rectifiers (SCR) are utilized extensively in power device applications because of the capability to switch from a very high impedance state to a very low impedance state. For the same reason, a properly designed SCR can also be a very efficient electrostatic discharge (ESD) protection device.
A semiconductor integrated circuit (IC) is generally susceptible to an electrostatic discharge (ESD) event that may damage or destroy the IC. An ESD event refers to a phenomenon of electrical discharge of a current (positive or negative) for a short duration in which a large amount of current is discharged through the IC. Protecting an IC from an ESD event, therefore, is an important factor to be considered in IC design. In deep sub-micron, or small geometry, complementary metal oxide silicon (CMOS) technology, the protection of an IC becomes an even more important issue due to the implementation of thin oxide layers in such ICs. As oxide layers become thinner, the voltage margin between oxide breakdown voltage and drain snapback breakdown voltage of a metal-oxide-silicon (“MOS”) transistor is reduced.
Integrated circuits (IC's) and other semiconductor devices are extremely sensitive to the high voltages that may be generated by contact with an ESD event. As such, ESD protection circuitry is essential for integrated circuits. An ESD event commonly results from the discharge of a high voltage potential (e.g., several kilovolts) and leads to pulses of high current (e.g., several amperes) of a short duration (e.g., 100 nanoseconds). An ESD event is generated within an IC, illustratively, by human contact with the leads of the IC or by electrically charged machinery being discharged in other leads of an IC. During installation of integrated circuits into products, these electrostatic discharges may destroy the IC's and thus require expensive repairs on the products, which could have been avoided by providing a mechanism for dissipation of the electrostatic discharge to which the IC may have been subjected.
The ESD problem has been especially pronounced in complementary metal oxide semiconductor (CMOS) field effect transistors. To protect against these over-voltage conditions, silicon controlled rectifiers (SCR) and other protection devices such as the grounded-gate NMOS have been incorporated within the circuitry of the CMOS IC to provide a discharge path for the high current produced by the discharge of the high electrostatic potential. Prior to an ESD event, the SCR is in a nonconductive state. Once the high voltage of an ESD event is encountered, the SCR then changes to a conductive state to shunt the current to ground. The SCR maintains this conductive state until the voltage is discharged to a safe level.
One type of SCR device that has shown promising results is a low voltage triggered SCR (LVTSCR), which is particularly robust in human-body model (HBM) events for bulk CMOS processes. FIG. 1 illustrates a cross-sectional diagram of one example of a prior art LVTSCR 100, wherein a drain junction formed by n+ region 122 is depicted across an N-well region 102 and a P-well region 104. In general, LVTSCR 100 includes a p+ region 110, an n+ region 120, an n+ region 122, a p+ region 124, and an n+ region 126. An anode 103 can be provided at nodes 136, 138, and 140, while a cathode is generally provided at nodes 128, 130, 132, and 134.
Note that electrically, nodes 136, 138, and 140 comprise the same electrical node or point. Similarly, 128, 130, 132, and 134 also electrical provide the same node or point. A poly region 106 is located adjacent oxide region 108, which together form a single NMOS finger 107. Poly region 106 is electrically connected to node 134 of cathode 101. In LVTSCR 100, the N-drain junction 122 is thus designed across respective N-well and P-well regions 102, 104 so that the trigger voltage of LVTSCR 100 can be lowered by the avalanche breakdown of an embedded one-finger ggNMOSFET's.
FIG. 2 illustrates a cross-sectional diagram of another example of a prior art LVTSCR 200, wherein a drain junction is connected to N+ diffusion within N-well by metals. LVTSCR 200 generally includes respective N-well and P-well regions 202, 204. Additionally, LVTSCR 200 includes a p+ region 210, an n+ region 220, an n+ region 222, an n+ region 223, a p+ region 224, and an n+ region 226. Note that p+ region 210, n+ region 220, and n+ region 222 are located within P-well 204, while n+ region 223, p+ region 224, and n+ region 226 are located within N-well 202. A cathode 201 is generally provided based on nodes 228, 230, 231, and 232. Similarly, an anode 203 is provided based on nodes 236, 238 and 240.
Nodes 228, 230, 231 and 232 electrically form the same node. Similarly, nodes 236, 238 and 240 also form a single electrical connection. In general, region 220 is connected to node 231. A poly region 206 is located adjacent oxide region 208, which together form a single NMOS finger 207. Region 206 is electrically connected to node 232 of cathode 201. Additionally, N+ region 222 is tied to a node 233, while n+ region 223 is tied to a node 235. Note that nodes 233 and 235 electrically comprise the same node. N+ region 222 and n+ region 223 are electrically connected to one another. Thus, instead of across N-well and P-well regions as is the case with the configuration depicted in FIG. 1, an N-drain junction formed by n+ region 222 and n+ region 223 can be separated into two different diffusions bus shorted by metals as depicted in FIG. 2.
One of the problems inherent with low voltage triggered SCR's, such as, for example, LVTSCR 100 and LVTSCR 200, is that due to a slow turn-on time in the lateral SCR, the lateral n-p-n BJT of ggNMOSFET's can become damaged as a result of associated positive and negative CDM events. Thus, although low voltage triggered SCR's are very robust in human-body model (HBM) stress conditions, such devices are very weak in CDM stress conditions. In order to overcome these problems and improve the CDM performance of low voltage triggered SCR's without scarifying HBM performance, it is believed that an improved low voltage triggered SCR should be developed utilizing NMOS inserted fingers as disclosed in further greater detail herein.